The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low resistance and capacitance interconnect properties, particularly where submicron inter-layer damascene interconnects (e.g., vias) and intra-layer interconnects having increasing large aspect ratios (narrow openings).
In particular, in forming a dual damascene by a via-first method where the via opening is first formed in one or more dielectric insulating layers followed by forming an overlying an encompassing trench opening for forming a metal interconnect line, several critical processing steps are required which entail exposing the low-K dielectric insulating layers to plasma assisted etching or ashing chemistries to etch openings and to remove photoresist layers.
For example, silicon oxide based low-K dielectric insulating layers have exhibited a tendency to interact with etching plasma to detrimentally affect the low-K dielectric insulating layer including increasing a dielectric constant as well as making it hydrophilic and more susceptible to moisture absorption during subsequent processing steps.
Approaches in the prior art to overcome some of these shortcomings has been to institute time-consuming baking processes to drive absorbed moisture out of the low-K dielectric insulating layer following wet cleaning and metal plating steps, such as copper electrochemical deposition (ECD). Other approaches have been to introduce a capping or protective layer over the dielectric insulating layer which also contributes to undesirably increased dielectric constants and capacitances but which does not protect a dielectric insulating layer with etched openings from degradation.
Problems with prior art approaches include the necessity of complicated etching, wet cleaning, and baking steps to overcome the problems of contamination and moisture (water) absorption in the dielectric insulating layer.
There is therefore a need in the semiconductor processing art to develop an improved dual damascene manufacturing process whereby the integrity and properties of dielectric insulating layers are improved while reducing a number of processing steps to achieve greater throughput.
It is therefore an object of the invention to provide an improved dual damascene manufacturing process whereby the integrity and properties of dielectric insulating layers are improved while reducing a number of processing steps to achieve greater throughput, in addition to overcoming other shortcomings and deficiencies in the prior art.